1. Field of the Invention
The present invention relates generally to methods for forming patterned conductor layers separated by patterned dielectric layers within microelectronics fabrications. More particularly, the present invention relates to dual damascene methods for forming patterned conductor layers separated by patterned dielectric layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and microelectronics device and patterned conductor layer dimensions have decreased, it has become increasingly common within the art of microelectronics fabrication to employ, interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics, conductor layers within microelectronics fabrications microelectronics dielectric layers formed of low dielectric constant dielectric materials. Such patterned microelectronics conductor layers often access within the microelectronics fabrications within which they are formed patterned conductor contact stud layers or patterned conductor interconnection stud layers. For the purposes of the present disclosure, low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant of less than about 3.0. For comparison purposes, dielectric layers formed employing conventional silicon oxide dielectric materials, silicon nitride dielectric materials or silicon oxynitride dielectric materials typically have dielectric constants in the range of from about 4.0 to about 7.0.
Microelectronics dielectric layers formed of low dielectric constant dielectric materials are desirable interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor layers within microelectronics fabrications since such dielectric layers formed from such low dielectric constant dielectric materials provide dielectric layers which assist in providing microelectronics fabrications exhibiting enhanced microelectronics fabrication speed, attenuated patterned microelectronics conductor layer parasitic capacitance, and attenuated patterned microelectronics conductor layer cross-talk.
Low dielectric constant dielectric materials which may be employed for forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications are typically materials with hydrogen and/or carbon content, such as but not limited to organic polymer spin-on-polymer dielectric materials (such as but not limited to polyimide organic polymer spin-on-polymer dielectric materials, poly-arylene-ether organic polymer spin-on-polymer dielectric materials, and fluorinated poly-arylene-ether organic polymer spin-on-polymer dielectric materials), amorphous carbon dielectric materials (such as but not limited to amorphous carbon and fluorinated amorphous carbon), and silsesqiuoxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon silsesquioxane spin-on-glass (SOG) dielectric materials, and carbon bonded fluorocarbon silsesquioxane spin-on-glass (SOG) dielectric materials).
While organic polymer spin-on-polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials are thus desirable within the art of microelectronics fabrication for forming patterned low dielectric constant microelectronics dielectric layers interposed between the patterns of patterned conductor layers which access patterned conductor stud layers within microelectronics fabrications, such microelectronics fabrication structures are often not formed entirely without problems. In particular, such microelectronics fabrication structures are typically formed employing an etch stop layer formed interposed between: (1) a patterned first dielectric layer through which is formed a patterned conductor stud layer; and (2) a patterned low dielectric constant dielectric layer which is formed adjoining the patterned conductor layer which contacts the patterned conductor stud layer. The etch stop layer typically assures optimal definition of the patterned conductor layer within respect to the patterned conductor stud layer. Unfortunately, the presence of such etch stop layers often provides additional microelectronics fabrication complexity within microelectronics fabrications within which are formed patterned conductor layers which contact patterned conductor stud layers.
It is thus towards the goal of forming microelectronics fabrication structures comprising patterned low dielectric constant dielectric layers separating patterned conductor layers which in turn contact patterned conductor stud layers, with attenuated microelectronics fabrication complexity, that the present invention is directed.
Various methods have been disclosed in the art of microelectronics fabrication for forming patterned microelectronics layers within microelectronics fabrications.
For example, Korczynski, in "Low-k dielectric integration cost modelling," Solid State Technology, Oct. 1997, pp. 123-28, discloses in general various methods and materials for forming patterned low dielectric constant dielectric layers interposed between the patterns of patterned conductor layers which in turn contact patterned conductor stud layers within microelectronics fabrications. Disclosed are standard patterned conductor layer formation and dielectric layer isolation methods and dual damascene patterned conductor layer formation and dielectric layer isolation methods.
In addition, Krishnan et al., in U.S. Pat. No. 5,380,546, discloses a maskiess method for forming a barrier layer surrounded metal feature within a planar insulator layer within a microelectronics fabrication. The barrier layer surrounded metal feature so formed is formed employing a planarizing method rather than a masking method.
Further, Ireland, in U.S. Pat. No. 5,466,639, discloses a dual damascene method for forming a patterned conductor layer contiguous with a patterned conductor stud layer within a semiconductor integrated circuit microelectronics fabrication. The dual damascene method employs a patterned mask layer formed interposed between a lower dielectric layer through which is formed the patterned conductor stud layer and an upper dielectric layer through which is formed the patterned conductor layer contiguous with the patterned conductor stud layer, where the upper dielectric layer and the lower dielectric layer are patterned employing a single reactive ion etch method.
Yet further, Havemann, in U.S. Pat. No. 5,565,384, discloses a method for forming within an integrated circuit microelectronics fabrication a self-aligned via through an inorganic dielectric layer to access a patterned conductor layer formed below the inorganic dielectric layer, where the patterned conductor layer has interposed at least partially between its patterns an organic containing dielectric layer. The patterned conductor layer and the organic dielectric layer are completely covered by the inorganic dielectric layer. The method employs an anisotropic etchant which is selective to the inorganic dielectric layer with respect to the organic dielectric layer, such that the organic dielectric layer serves as an etch stop layer when etching the self-aligned via through the inorganic dielectric layer, thus avoiding overetching of the organic dielectric layer.
Still yet further, Huang et al., in U.S. Pat. No. 5,635,423 also discloses a dual damascene method for forming a patterned conductor layer contiguous with a patterned conductor stud layer within a semiconductor integrated circuit microelectronics fabrication. The dual damascene method employs a blanket mask layer formed interposed between a lower dielectric layer through which is formed the patterned conductor stud layer and an upper dielectric layer through which is formed the patterned conductor layer contiguous with the patterned conductor stud layer, where the upper dielectric layer and the lower dielectric layer are sequentially patterned employing separate reactive ion etch (RIE) methods.
Finally, Avanzino et al., in U.S. Pat. No. 5,686,354, discloses yet another dual damascene method for forming a patterned conductor layer contiguous with a patterned conductor stud layer within a microelectronics fabrication. The dual damascene method employs a single dielectric layer sequentially: (1) partially patterned employing a first etch method to form a trench within the single dielectric layer; and (2) subsequently completely patterned employing a second etch method and hard mask layer exposing a portion of a floor within the trench, to define with sharp sidewall edges the patterned conductor stud layer through the single dielectric layer.
Desirable in the art of microelectronics fabrication are methods through which there may be formed within microelectronics fabrications low dielectric constant dielectric layers interposed between the patterns of patterned conductor layers which in turn contact patterned conductor stud layers, with attenuated process complexity.
It is towards the foregoing object that the present invention is both generally and more specifically directed.